Scalable Cross-Architecture Predictions of Memory Latency for Scientific Applications

Abstract The gap between processor and memory speeds has been growing with each new generation of microprocessors. As a result, memory hierarchy response has become a critical factor limiting application performance. For this reason, we have been working to model the impact of memory access latency on program performance. This poster presents a method for characterizing an application's data access patterns in a machine independent fashion. We collect data reuse distance histograms for each memory reference in a program during repeated executions with small data inputs. Then, we model the structure and scaling of each reference's reuse distance as a function of problem size. This approach enables us to predict the number of compulsory and capacity cache misses at the instruction level for architectures and problem sizes that we did not measure. In conjunction with our reuse distance models, we use a probabilistic model to estimate the number of conflict misses for set-associative caches. We validate our approach by comparing our predictions against measurements using hardware performance counters, for several benchmarks over a large range of problem sizes. Poster Contributors: Gabriel Marin and John Mellor-Crummey Poster Presented by Gabriel Marin

Click here to get the file